Semiconductor package and manufacturing method thereof

ABSTRACT

A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.

RELATED APPLICATIONS

This is a Continuation of U.S. application Ser. No. 12/292,813, filedNov. 6, 2008, which was a Continuation of U.S. application Ser. No.11/898,717, filed Sep. 14, 2007, which was a Continuation-in-part ofU.S. application Ser. No. 11/882,194, filed Jul. 31, 2007, which claimsthe benefit of Taiwan application No. 95146945, filed Dec. 14, 2006, thesubject matters of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates in general to a semiconductor package andmanufacturing method thereof, and more particularly to a semiconductorpackage whose lead frame can be independently isolated and transportedduring the manufacturing process.

2. Description of the Related Art

Along with the advance in science and technology, the demand for variouselectronic products is booming. Meanwhile, as miniaturization isexpected of electronic products by consumers, the semiconductor element,a crucial element used in an electronic product, is also directedtowards the design of miniaturization, and the reduction in the pitchand width of the circuit of a semiconductor element has always been animportant direction in the semiconductor industry. However, in additionto the reduction in the pitch and width of the circuit inside asemiconductor chip, the chip package carrying the signal and extended tothe external also plays an important part in the miniaturization of asemiconductor element. If the circuit and pitch of a semiconductorpackage can not be effectively reduced, the miniaturization in the sizeof a semiconductor element using the same will be very limited.

For example, the thickness of a metallic trace of a conventional packagenormally ranges between 120 to 250 micrometers, and a package trace isformed after the process of micro-filming, exposure and etching.However, the etching process restricts the pitch and width of a circuit,and the undercutting effect will affect the reliability of the packagetrace. Therefore, the conventional lead frame of the package trace isnot suitable to the miniaturization in semiconductor element.

Thus, how to resolve the above problem of element miniaturization andsimplify the manufacturing process of the package has become animportant direction in the research and development of semiconductorpackage.

SUMMARY OF THE INVENTION

According to a first aspect of an embodiment of the present invention, asemiconductor package is provided. The semiconductor package comprises afirst insulating layer and a plurality of package traces, wherein aplurality of holes are disposed on a first surface of the firstinsulating layer, and the package traces are embedded in the insulatinglayer and connected to another end of the holes.

According to an aspect of another embodiment of the present invention, asemiconductor package is provided. The semiconductor package comprises afirst insulating layer, a plurality of positioning units and a pluralityof package traces. The elastic modulus of the first insulating layer islarger than 1.0 GPa. The positioning units are disposed on the firstinsulating layer. The package traces are disposed under the positioningunit.

According to an aspect of another embodiment of the present invention, amanufacturing method of a semiconductor package is provided. Themanufacturing method comprises the following steps. Firstly, a carrieris provided. Next, a plurality of traces are formed on the carrier.Then, a first insulating layer is formed on the traces. Afterwards, aplurality of positioning units are formed on a first surface of thefirst insulating layer next, wherein the positioning unit contacts thetrace directly.

According to an aspect of another embodiment of the present invention, amethod of manufacturing a semiconductor package is provided. The methodof manufacturing the semiconductor package comprises the followingsteps. Firstly, a carrier is provided. Then, a plurality of electricallyisolated package trace layout units are formed by a first conductivelayer, wherein the package trace layout unit is formed by a plurality ofelectrically isolated package traces. Afterwards, a patterned secondconductive layer is formed on the first conductive layer. Then a firstinsulating layer is formed by a molding material and embedded in thefirst conductive layer and the second conductive layer. After that, partof the carrier is selectively removed.

The invention will become apparent from the following detaileddescription of the preferred but non-limiting embodiments. The followingdescription is made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 to FIG. 8 are process flowcharts of manufacturing an independentsemiconductor package according to a first embodiment of the invention.

FIG. 9 to FIG. 14 are detailed flowcharts of manufacturing andconnecting an independent semiconductor package to a chip exemplified bythree different chip packages according to a first embodiment of theinvention.

FIG. 15 is an example of the first embodiment of the invention used in amulti-chip package.

FIG. 16 to FIG. 17 are detailed diagrams before the package elements ofthe first embodiment of the invention are packaged.

FIG. 18 to FIG. 25 are diagrams of manufacturing an independentsemiconductor package according to a second embodiment of the invention.

FIG. 26 to FIG. 36 are diagrams of manufacturing an independentsemiconductor package according to a third embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION First Embodiment

Referring to FIG. 1 onwards, process flowcharts of manufacturing anindependent semiconductor package according to a first embodiment of theinvention are shown. Firstly, a carrier 10 is provided. In the presentembodiment of the invention, the carrier 10 is a steel piece. Then,referring to FIG. 2, a photo-resist layer 11 is formed on the carrier 10first, and further shaped as a patterned photo-resist layer 11′asindicated in FIG. 3.

Referring to FIG. 4, a conductive layer 20 is formed in the empty partof the photo-resist layer 11′, wherein the thickness of the conductivelayer 20 normally between ranges 0.01 to 0.4 mm, but preferably rangesbetween 0.025 to 0.035 mm. In the present embodiment of the invention,the conductive layer 20 is formed by electroplating. As indicated inFIG. 5, the photo-resist layer 11′ is removed, but the conductive layer20 (the first conductive layer) is left and used as package traces notthe traces inside a semiconductor chip. In the present embodiment of theinvention, a plurality of package traces formed by the conductive layer20 are preferably electrically isolated and used as a package tracelayout unit. In practical application, the package traces areelectrically connected to each other. During the process of formation, aplurality of package trace layout units are formed, and each packagetrace layout unit substantially has the same pattern and individuallycorresponds to a to-be-packaged chip.

Referring to FIG. 6, a mold 23 is provided, wherein the mold 23 has aplurality of protrusions corresponding to the position of the tracelayer 20. Then, an insulating material is infused to form a firstinsulating layer 21, wherein the thickness of the first insulating layer21 normally ranges between 0.1 to 0.4 mm, but preferably ranges between0.18 to 0.22 mm. As indicated in FIG. 7, a plurality of package tracesare embedded in the first insulating layer 21 or disposed in the firstinsulating layer 21 and extended to a surface of the first insulatinglayer 21. In the present embodiment of the invention, the insulatingmaterial is a molding material, the elastic modulus of the insulatingmaterial is larger than 1.0 GPa, and preferably the CTE value of theinsulating material is less than 10 ppm. In practical application, thefirst insulating layer 21 is not necessarily limited to one layer. Anyone who is skilled in the technology of the invention can use severalmaterials to compose a compound insulating layer in several times offormation or use the same material to compose an insulating layer inseveral times of formation, and such modifications are still within thescope of protection of the invention. However, in the present embodimentof the invention, the first insulating layer 21 is formed from a singlematerial, such that the package traces are embedded in the firstinsulating layer 21. That is, the height of the first insulating layer21 must be larger than the height of the package traces.

As a plurality of protrusions disposed on the mold 23 correspond to thetrace layer 20, a plurality of holes 22 are formed on a surface of thefirst insulating layer 21. Referring to FIG. 8, the mold 23 and thecarrier 10 are removed, and a semiconductor package that can betransported independently is formed. In the present embodiment of theinvention, the other end of the holes 22 contacts the package trace ofthe trace layer 20, wherein the holes used as positioning units forconnecting the conductors are made from the trace layer 20.

Referring to FIG. 9, an independent semiconductor package manufacturedaccording to FIG. 8 is connected to a chip 31 via a second conductor. Inthe present embodiment of the invention, the second conductor isconnected to the chip 31 via a solder 33 and a pillar bump 32. Besides,as indicated in FIG. 10, the hole 22 can be fully or partly filled witha conductive material, such as nickel, gold, copper or solder, to form asecond conductive layer 41. In the present embodiment of the invention,the conductive material is formed by solder 41 to facilitate subsequentprocessing.

Referring to FIG. 11, the conductor 42 is fixed on the independentsemiconductor package via position-setting of the holes 22, such thatthe signal of the he chip 31 is transmitted externally via pillar bump32, the solder 33, the trace layer 20, and the conductor 42. In thepresent embodiment of the invention, the conductor 42 is a solder ballor a trace and the conductor 42 could be used to connect to printedcircuit board (PC Board) or another layer of receiving substrate. Toavoid the solder of the solder ball flowing everywhere when melted, thepositioning unit limits is for confining the solder to be within thehole 22. In the present embodiment of the invention, the positioningunit is a hole 22, which can be a run through hole or an indent only.

The solder 41 enables the electrically connection between the conductor42 and the trace layer 20 even more tightly, and avoids the occurrenceof bubbles which occurs when a solder ball is used as the conductor 42but can not completely fill up the hole 22.

On the other hand, the independent semiconductor package and the packageof the chip 31 can be flexible. Referring to FIG. 12, an insulatingmaterial, such as an encapsulating material, can be used as a secondinsulating layer 51 and infused to the chip 31 to encapsulate the pillarbump 32 but exposes the chip 31. Or, as indicated in FIG. 13, the secondinsulating layer 52 encapsulates the pillar bump 32 and the chip 31 butexposes the upper surface of the chip 31. Or, as indicated in FIG. 14,the second insulating layer 53 encapsulates the pillar bump 32 but isaligned with the chip 31.

Besides, the semiconductor package is also used in a multi-chip package.Referring to FIG. 15, a space 72 permitting the chip 61 to be fixed andconnected to the trace is disposed in addition to the hole of the firstinsulating layer, and the chip is connected to the solder ball via ahole 22′.

Referring to FIG. 16, a perspective of a lead frame according to a firstembodiment of the invention is shown. FIG. 16 is bottom view of FIG. 8,wherein the package trace layout unit 80 formed by a first conductivelayer is embedded in the first insulating layer 21, and a plurality offiducial marks 90 are used for positioning a lead frame when the chip ispackaged. In the present embodiment of the invention, the shape ofindividual package trace layout unit 80 is indicated in FIG. 17. Apackage trace layout unit 80 comprises a plurality of electricallyisolated package traces to form the pattern of a package trace layoutunit and correspond to a to-be-packaged chip, wherein smaller chips areelectrically connected via the conductive dots 84, and larger chips areelectrically connected via the conductive dots 74. Thus, it can be usedas the lead frame of different sized chips in the present embodiment ofthe invention. As indicated in FIG. 16 and FIG. 17, the package tracelayout units 80 substantially have the same pattern, and the packagetrace layout units 80, isolated between each other, are arranged in amatrix and embedded in the first insulating layer 21.

Each package trace layout unit 80 preferably has a fan-in or fan-outpattern. The first conductive layer 20 and the second conductive layer41 can have different pitches to achieve the function of fine pitch.

Second Embodiment

Referring to FIG. 18 and onwards, a method of manufacturing asemiconductor package according to a second embodiment of the inventionis shown. Firstly, a carrier 19 is provided, wherein the carrier 19 ismade from copper in the present embodiment of the invention. Like FIG. 1to FIG. 4 of the first embodiment, other manufacturing methods obtainthe stage result as indicated in FIG. 18, a patterned first conductivelayer 20′ is formed on the carrier 19.

Referring to FIG. 19, a layer photo-resist layer 25 is coated on thefirst conductive layer 20′, and a hole 27′ is formed on the patternedphoto-resist layer 25. Referring to FIG. 20, a second conductive layer27 is formed in the hole 27′. In the present embodiment of theinvention, the second conductive layer 27 is formed by way ofelectroplating and is substantially flat nor protruded from the surfaceof the first insulating layer 28.

The photo-resist layer 25 is removed such that a patterned firstconductive layer 20′ and a second conductive layer 27 are obtained asindicated in FIG. 21. Referring to FIG. 22, a molding material isinjected to form a first insulating layer 28, such that the patternedfirst conductive layer 20′ and the second conductive layer 27 areembedded in the first insulating layer 28. In the present embodiment ofthe invention, the molding material used to form the first insulatinglayer 28 is epoxy resin, the elastic modulus of the molding material isgreater than 1.0 GPa, but the CTE value of the elastic modulus is lessthan 10 ppm.

By way of etching, the carrier 19 is removed to obtain a semiconductorpackage before package as indicated in FIG. 23. The application of theunpackaged semiconductor package is indicated in FIG. 24, and theunpackaged semiconductor package can be connected to the chip 31′ viathe solder 33′, the pillar bump 32′.

Besides, the second conductive layer 27 can be pre-treated to resolvethe resin residue problem arising in a QFN package when the tape isremoved.

Referring to FIG. 25, a conductive protrusion 39 can be disposed on thefirst conductive layer 20′ of the package trace layout. The conductiveprotrusion 39 can be made from silver, gold, other metals or conductivematerials, and the part of the package trace layout directly atop of theconductive protrusion is the molding material of the first insulatinglayer 28. Thus, when the unpackaged semiconductor package is used inconventional wiring bonding, the trace can be connected to theconductive protrusion 39 such that the lead frame neighbors the chippackage as close as possible and will not wobble when connected to thetraces, hence increasing the efficiency of bonding the wire to the chip.

Third Embodiment

Referring to FIG. 26 and onwards, a method of manufacturing asemiconductor package according to a third embodiment of the inventionis shown. Firstly, a carrier 19′ is provided, wherein the carrier 19′ ismade from copper in the present embodiment of the invention. Like FIG. 1to FIG. 4 of the first embodiment, other manufacturing methods obtainthe stage result as indicated in FIG. 26, a patterned first conductivelayer 20′ is formed on the carrier 19′.

Referring to FIG. 27, a layer photo-resist layer 25 is coated on thefirst conductive layer 20′, and a hole 27′ is formed on the patternedphoto-resist layer 25. Referring to FIG. 28, a second conductive layer27 is formed in the hole 27′. In the present embodiment of theinvention, the second conductive layer 27 is formed by way ofelectroplating and is substantially flat nor protruded from the surfaceof the first insulating layer 28.

The photo-resist layer 25 is removed such that a patterned firstconductive layer 20′ and a second conductive layer 27 are obtained asindicated in FIG. 29. Referring to FIG. 30, a molding material isinjected to form a first insulating layer 28, such that the patternedfirst conductive layer 20′ and the second conductive layer 27 areembedded in the first insulating layer 28. In the present embodiment ofthe invention, the molding material used to form the first insulatinglayer 28 is epoxy resin, the elastic modulus of the molding material isgreater than 1.0 GPa, but the CTE value of the elastic modulus is lessthan 10 ppm.

By way of etching, part of the carrier 19′ is selectively removed toobtain a semiconductor package before package as indicated in FIGS.31-35.

Referring to FIG. 31, a photo resist layer 81 is formed on the carrier19′. Then the photo resist layer 81 is exposed via a mask 82 having atleast a first opening 82 a and at least a second opening 82 b as shownin FIG. 32. And a patterned photo resist layer 81 having at least afirst opening 81 a and at least a second opening 81 b is obtained asindicated in FIG. 33. Wherein the first opening 81 a and the firstopening 82 a are corresponding with the inside area of the firstinsulating layer 28, and the second opening 81 b and the second opening82 b are corresponding with the outside area of the first insulatinglayer 28.

Afterwards, referring to FIG. 34, the carrier 19′ is etched by takingthe patterned photo resist layer 81 as a mask. Wherein the carrier 19′and part of the first conductive layer 20′ are etched simultaneously sothat the surface 20′a of the first conductive layer 20′ and the surface28′a of the first insulating layer 28 a are not located at the sameplane. Then, the patterned photo resist layer 81 is removed so that anenforcement ring 19′c and at least a positioning hole 19′b are formed onthe carrier 19′ as indicated in FIG. 35.

Please refer to FIG. 36. After part of the carrier 19′ is selectivelyremoved, the enforcement ring 19′c is formed on the peripheral area ofthe carrier 19′ and the positioning hole 19′b are formed in theenforcement ring 19′c. The semiconductor package can be carried via theenforcement ring 19′c and the position hole 19′b without touching thefirst insulating layer 28 or the second conductive layer 27. Therefore,the scraping damage of the semiconductor package can be prevented.

The conductive layer 20 or 20′ (the package trace) is formed during themanufacturing process without applying extra process such asmicro-filming, exposure and etching on the conductive layer, so that theconductive layer is not restricted by the etching pitch and thereliability of the package trace will not be affected by undercutting.However, the package trace meets the requirement of miniaturization inthe semiconductor element better.

The package trace layout unit has a fan-in or fan-out pattern to achievethe function of fine pitch.

Moreover, the hole 22 (the positioning unit) makes the positioningsetting of connecting the solder ball to the package element moreprecisely, and avoids the overflowing of the solder when melted.

Besides, the mold 23, and hole 22 (the positioning unit) are formed byusing the material of the first insulating layer 21 directly, such thatthe first insulating layer 21 and the positioning unit are formed by onefilling of the molding material, largely simplifying the manufacturingprocess of the semiconductor package.

Moreover, according to FIG. 11, with the disposition of the packagetrace 20, the pitch between the solder balls can be larger than thepitch between the chip bumps 32. Therefore, the technology of theinvention can be applied to a manufacturing process with a lowerrequirement of the pitch.

Furthermore, the first insulating layer 21 uses a molding material as acarrier for the package trace pattern, therefore the package tracepatterns are not connected by metallic traces and are different formconventional lead frame which has traces for connecting the packagetrace patterns. The insulating layer between the traces of the leadframe is simply used for insulating purpose and can not be used as acarrier. As a result, in the embodiments of the invention does not havethe connecting traces for connecting the lead frame patterns, and eachpackage has an individual pattern, and is easier for cutting.

In a conventional chip, the package traces are connected via metallictraces, therefore the package traces must be divided first before thechip can be tested individually. In the above embodiments, as eachpackage trace pattern is electrically isolated and does not havemetallic traces for connection, the chip still can be tested even afterthe chip is connected to the package trace, largely saving time and costfor testing.

While the invention has been described by way of example and in terms ofa preferred embodiment, it is to be understood that the invention is notlimited thereto. On the contrary, it is intended to cover variousmodifications and similar arrangements and procedures, and the scope ofthe appended claims therefore should be accorded the broadestinterpretation so as to encompass all such modifications and similararrangements and procedures. For examples, the first insulating layer21, is not necessarily limited to one layer. Any one who is skilled inthe technology of the invention can use several materials to compose acompound insulating layer in several times of formation or use the samematerial to compose an insulating layer in several times of formation,and such modifications are still within the scope of protection of theinvention which is defined in the appended claims.

What is claimed is:
 1. A semiconductor package, comprising: a packagetrace layout comprising a plurality of package traces; an insulatinglayer having a first surface and a second surface opposite the firstsurface, wherein the plurality of package traces are embedded in theinsulating layer between the first surface and the second surface, thepackage trace layout is entirely exposed on the first surface of theinsulating layer; wherein the package trace layout further comprises atleast two different patterns of conductive dots on the first surface ofthe insulating layer that is used to connect to semiconductor chips ofdifferent sizes.
 2. The semiconductor package according to claim 1,wherein one or more package traces comprise at least two conductive dotsand each conductive dot corresponds to a different pattern of conductivedots for connecting to semiconductor chips of different sizes.
 3. Thesemiconductor package according to claim 1, wherein the plurality ofpackage traces is mutually isolated from one another.